/*
 * Copyright (C) 2016 MediaTek Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 */

#ifndef __MT_IOMMU_PORT_H__
#define __MT_IOMMU_PORT_H__
/*
 * this header file is only used for mtk_iomm module
 * the definition of header file is platform dependency.
 */
//enable this option if M4U new design of multiple bank
//#define IOMMU_DESIGN_OF_BANK

struct mtk_iommu_port {
	char *name;
	unsigned m4u_id: 2;
	unsigned m4u_slave: 2;
	unsigned larb_id: 6;
	unsigned larb_port: 8;
	unsigned tf_id: 14;     /* 14 bits */
	bool enable_tf;
	mtk_iommu_fault_callback_t fault_fn;
	void *fault_data;
};
#define MTK_IOMMU_PORT_INIT(name, id, slave, larb, tf_larb, port)  {\
	name, id, slave, larb, port, (((tf_larb)<<7)|((port)<<2)), 1\
}

#define SLAVE_L0 (0)
#define SLAVE_L1 (0)
#define SLAVE_L2 (0)
#define SLAVE_L3 (0)
#define SLAVE_L4 (0)
#define SLAVE_L5 (0)
#define SLAVE_L7 (0)
#define SLAVE_L8 (0)
#define SLAVE_L9 (0)
#define SLAVE_L11 (0)
#define SLAVE_L13 (0)
#define SLAVE_L14 (0)
#define SLAVE_L16 (0)
#define SLAVE_L17 (0)
#define SLAVE_L18 (0)
#define SLAVE_L19 (0)
#define SLAVE_L20 (0)
#define SLAVE_APU (0)
#define SLAVE_CCU_DISP (0)
#define SLAVE_CCU_MDP (0)

/* MM_IOMMU AXI_ID */
#define TF_LARB_L0 (0x0)
#define TF_LARB_L1 (0x4)
#define TF_LARB_L2 (0x0)
#define TF_LARB_L3 (0x4)
#define TF_LARB_L4 (0x8)
#define TF_LARB_L5 (0x8)
#define TF_LARB_L7 (0xc)
#define TF_LARB_L8 (0xc)
#define TF_LARB_L9 (0x10)
#define TF_LARB_L11 (0x10)
#define TF_LARB_L13 (0x19)
#define TF_LARB_L14 (0x19)
#define TF_LARB_L16 (0x1c)
#define TF_LARB_L17 (0x1c)
#define TF_LARB_L18 (0x14)
#define TF_LARB_L19 (0x14)
#define TF_LARB_L20 (0x15)
#define TF_APU (0x0)
#define TF_CCU_DISP (0x18)
#define TF_CCU_MDP (0x18)

int mtk_iommu_larb_port_count[] = {
	15, 15, 6, 6, 11,//0~4
	8, 0, 27, 27, 29, //5~9
	0, 29, 0, 12, 6, //10~14
	0, 17, 17, 17, 4, //15~19
	6, 3, 1, 1 //20~23
};

int mtk_iommu_larb_distance[] = {
	0, 15, 30, 36, 42, //0~4
	53, -1, 61, 88, 115, //5~9
	-1, 144, -1, 173, 185, //10~14
	-1, 191, 208, 225, 242,//15~19
	246, 252, 255, 256 //20~23
};

struct mtk_iommu_port iommu_port[] = {
	/*Larb0 */
	MTK_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", 0,
		SLAVE_L0, 0, TF_LARB_L0, 0),
	MTK_IOMMU_PORT_INIT("L0_MDP_RDMA4", 0,
		SLAVE_L0, 0, TF_LARB_L0, 1),
	MTK_IOMMU_PORT_INIT("L0_OVL_RDMA0_HDR", 0,
		SLAVE_L0, 0, TF_LARB_L0, 2),
	MTK_IOMMU_PORT_INIT("L0_OVL_2L_RDMA1_HDR", 0,
		SLAVE_L0, 0, TF_LARB_L0, 3),
	MTK_IOMMU_PORT_INIT("L0_OVL_2L_RDMA3_HDR", 0,
		SLAVE_L0, 0, TF_LARB_L0, 4),
	MTK_IOMMU_PORT_INIT("L0_OVL_RDMA0", 0,
		SLAVE_L0, 0, TF_LARB_L0, 5),
	MTK_IOMMU_PORT_INIT("L0_OVL_2L_RDMA1", 0,
		SLAVE_L0, 0, TF_LARB_L0, 6),
	MTK_IOMMU_PORT_INIT("L0_OVL_2L_RDMA3", 0,
		SLAVE_L0, 0, TF_LARB_L0, 7),
	MTK_IOMMU_PORT_INIT("L0_OVL_RDMA1_SYSRAM", 0,
		SLAVE_L0, 0, TF_LARB_L0, 8),
	MTK_IOMMU_PORT_INIT("L0_OVL_2L_RDMA0_SYSRAM	", 0,
		SLAVE_L0, 0, TF_LARB_L0, 9),
	MTK_IOMMU_PORT_INIT("L0_OVL_2L_RDMA2_SYSRAM", 0,
		SLAVE_L0, 0, TF_LARB_L0, 10),
	MTK_IOMMU_PORT_INIT("L0_DISP_WDMA0", 0,
		SLAVE_L0, 0, TF_LARB_L0, 11),
	MTK_IOMMU_PORT_INIT("L0_DISP_RDMA0", 0,
		SLAVE_L0, 0, TF_LARB_L0, 12),
	MTK_IOMMU_PORT_INIT("L0_DISP_UFBC_WDMA0", 0,
		SLAVE_L0, 0, TF_LARB_L0, 13),
	MTK_IOMMU_PORT_INIT("L0_DISP_FAKE0	", 0,
		SLAVE_L0, 0, TF_LARB_L0, 14),
	/*Larb1 */
	MTK_IOMMU_PORT_INIT("L1_DISP_POSTMASK1", 0,
		SLAVE_L1, 1, TF_LARB_L1, 0),
	MTK_IOMMU_PORT_INIT("L1_MDP_RDMA5", 0,
		SLAVE_L1, 1, TF_LARB_L1, 1),
	MTK_IOMMU_PORT_INIT("L1_OVL_RDMA1_HDR", 0,
		SLAVE_L1, 1, TF_LARB_L1, 2),
	MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0_HDR", 0,
		SLAVE_L1, 1, TF_LARB_L1, 3),
	MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA2_HDR", 0,
		SLAVE_L1, 1, TF_LARB_L1, 4),
	MTK_IOMMU_PORT_INIT("L1_OVL_RDMA1", 0,
		SLAVE_L1, 1, TF_LARB_L1, 5),
	MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0", 0,
		SLAVE_L1, 1, TF_LARB_L1, 6),
	MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA2", 0,
		SLAVE_L1, 1, TF_LARB_L1, 7),
	MTK_IOMMU_PORT_INIT("L1_OVL_RDMA0_SYSRAM", 0,
		SLAVE_L1, 1, TF_LARB_L1, 8),
	MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA1_SYSRAM", 0,
		SLAVE_L1, 1, TF_LARB_L1, 9),
	MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA3_SYSRAM", 0,
		SLAVE_L1, 1, TF_LARB_L1, 10),
	MTK_IOMMU_PORT_INIT("L1_DISP_WDMA1", 0,
		SLAVE_L1, 1, TF_LARB_L1, 11),
	MTK_IOMMU_PORT_INIT("L1_DISP_RDMA1", 0,
		SLAVE_L1, 1, TF_LARB_L1, 12),
	MTK_IOMMU_PORT_INIT("L1_DISP_UFBC_WDMA1", 0,
		SLAVE_L1, 1, TF_LARB_L1, 13),
	MTK_IOMMU_PORT_INIT("L1_DISP_FAKE1", 0,
		SLAVE_L1, 1, TF_LARB_L1, 14),
	/*Larb2 */
	MTK_IOMMU_PORT_INIT("L2_MDP_RDMA0", 1,
		SLAVE_L2, 2, TF_LARB_L2, 0),
	MTK_IOMMU_PORT_INIT("L2_MDP_RDMA2", 1,
		SLAVE_L2, 2, TF_LARB_L2, 1),
	MTK_IOMMU_PORT_INIT("L2_MDP_WROT0", 1,
		SLAVE_L2, 2, TF_LARB_L2, 2),
	MTK_IOMMU_PORT_INIT("L2_MDP_WROT2", 1,
		SLAVE_L2, 2, TF_LARB_L2, 3),
	MTK_IOMMU_PORT_INIT("L2_MDP_FILMGRAIN0", 1,
		SLAVE_L2, 2, TF_LARB_L2, 4),
	MTK_IOMMU_PORT_INIT("L2_MDP_FAKE0", 1,
		SLAVE_L2, 2, TF_LARB_L2, 5),
	/*Larb3 */
	MTK_IOMMU_PORT_INIT("L3_MDP_RDMA1", 1,
		SLAVE_L3, 3, TF_LARB_L3, 0),
	MTK_IOMMU_PORT_INIT("L3_MDP_RDMA3", 1,
		SLAVE_L3, 3, TF_LARB_L3, 1),
	MTK_IOMMU_PORT_INIT("L3_MDP_WROT1", 1,
		SLAVE_L3, 3, TF_LARB_L3, 2),
	MTK_IOMMU_PORT_INIT("L3_MDP_WROT3", 1,
		SLAVE_L3, 3, TF_LARB_L3, 3),
	MTK_IOMMU_PORT_INIT("L3_MDP_FILMGRAIN1", 1,
		SLAVE_L3, 3, TF_LARB_L3, 4),
	MTK_IOMMU_PORT_INIT("L3_MDP_FAKE1", 1,
		SLAVE_L3, 3, TF_LARB_L3, 5),
	/*Larb4 */
	MTK_IOMMU_PORT_INIT("L4_VDEC_MC_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 0),
	MTK_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 1),
	MTK_IOMMU_PORT_INIT("L4_VDEC_PP_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 2),
	MTK_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 3),
	MTK_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 4),
	MTK_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 5),
	MTK_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 6),
	MTK_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 7),
	MTK_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 8),
	MTK_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 9),
	MTK_IOMMU_PORT_INIT("L4_VDEC_RG_CTRL_DMA_EXT_MDP", 1,
		SLAVE_L4, 4, TF_LARB_L4, 10),
	/*Larb5 */
	MTK_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 0),
	MTK_IOMMU_PORT_INIT("L5_VDEC_LAT0_VLD2_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 1),
	MTK_IOMMU_PORT_INIT("L5_VDEC_LAT0_AVC_MV_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 2),
	MTK_IOMMU_PORT_INIT("L5_VDEC_LAT0_PRED_RD_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 3),
	MTK_IOMMU_PORT_INIT("L5_VDEC_LAT0_TILE_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 4),
	MTK_IOMMU_PORT_INIT("L5_VDEC_LAT0_WDMA_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 5),
	MTK_IOMMU_PORT_INIT("L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 6),
	MTK_IOMMU_PORT_INIT("L5_VDEC_UFO_ENC_EXT_DISP", 0,
		SLAVE_L5, 5, TF_LARB_L5, 7),
	/*Larb7 */
	MTK_IOMMU_PORT_INIT("L7_VENC_RCPU_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 0),
	MTK_IOMMU_PORT_INIT("L7_VENC_REC_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 1),
	MTK_IOMMU_PORT_INIT("L7_VENC_BSDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 2),
	MTK_IOMMU_PORT_INIT("L7_VENC_SV_COMV_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 3),
	MTK_IOMMU_PORT_INIT("L7_VENC_RD_COMV_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 4),
	MTK_IOMMU_PORT_INIT("L7_VENC_NBM_RDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 5),
	MTK_IOMMU_PORT_INIT("L7_VENC_NBM_RDMA_LITE_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 6),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 7),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_C_RDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 8),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_Q_TABLE_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 9),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_BSDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 10),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_WDMA0_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 11),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_BSDMA0_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 12),
	MTK_IOMMU_PORT_INIT("L7_VENC_NBM_WDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 13),
	MTK_IOMMU_PORT_INIT("L7_VENC_NBM_WDMA_LITE_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 14),
	MTK_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 15),
	MTK_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 16),
	MTK_IOMMU_PORT_INIT("L7_VENC_REF_LUMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 17),
	MTK_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 18),
	MTK_IOMMU_PORT_INIT("L7_VENC_SUB_R_LUMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 19),
	MTK_IOMMU_PORT_INIT("L7_VENC_SUB_W_LUMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 20),
	MTK_IOMMU_PORT_INIT("L7_VENC_FCS_NBM_RDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 21),
	MTK_IOMMU_PORT_INIT("L7_VENC_FCS_NBM_WDMA_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 22),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_WDMA1_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 23),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_BSDMA1_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 24),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_HUFF_OFFSET1_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 25),
	MTK_IOMMU_PORT_INIT("L7_JPGENC_HUFF_OFFSET0_DISP", 0,
		SLAVE_L7, 7, TF_LARB_L7, 26),
	/*Larb8 */
	MTK_IOMMU_PORT_INIT("L8_VENC_RCPU_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 0),
	MTK_IOMMU_PORT_INIT("L8_VENC_REC_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 1),
	MTK_IOMMU_PORT_INIT("L8_VENC_BSDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 2),
	MTK_IOMMU_PORT_INIT("L8_VENC_SV_COMV_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 3),
	MTK_IOMMU_PORT_INIT("L8_VENC_RD_COMV_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 4),
	MTK_IOMMU_PORT_INIT("L8_VENC_NBM_RDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 5),
	MTK_IOMMU_PORT_INIT("L8_VENC_NBM_RDMA_LITE_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 6),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_Y_RDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 7),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_C_RDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 8),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_Q_TABLE_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 9),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_BSDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 10),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_WDMA0_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 11),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_BSDMA0_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 12),
	MTK_IOMMU_PORT_INIT("L8_VENC_NBM_WDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 13),
	MTK_IOMMU_PORT_INIT("L8_VENC_NBM_WDMA_LITE_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 14),
	MTK_IOMMU_PORT_INIT("L8_VENC_CUR_LUMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 15),
	MTK_IOMMU_PORT_INIT("L8_VENC_CUR_CHROMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 16),
	MTK_IOMMU_PORT_INIT("L8_VENC_REF_LUMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 17),
	MTK_IOMMU_PORT_INIT("L8_VENC_REF_CHROMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 18),
	MTK_IOMMU_PORT_INIT("L8_VENC_SUB_R_LUMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 19),
	MTK_IOMMU_PORT_INIT("L8_VENC_SUB_W_LUMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 20),
	MTK_IOMMU_PORT_INIT("L8_VENC_FCS_NBM_RDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 21),
	MTK_IOMMU_PORT_INIT("L8_VENC_FCS_NBM_WDMA_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 22),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_WDMA1_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 23),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_BSDMA1_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 24),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_HUFF_OFFSET1_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 25),
	MTK_IOMMU_PORT_INIT("L8_JPGENC_HUFF_OFFSET0_MDP", 1,
		SLAVE_L8, 8, TF_LARB_L8, 26),
	/*Larb9 */
	MTK_IOMMU_PORT_INIT("L9_IMG_IMGI_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 0),
	MTK_IOMMU_PORT_INIT("L9_IMG_IMGBI_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 1),
	MTK_IOMMU_PORT_INIT("L9_IMG_DMGI_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 2),
	MTK_IOMMU_PORT_INIT("L9_IMG_DEPI_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 3),
	MTK_IOMMU_PORT_INIT("L9_IMG_ICE_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 4),
	MTK_IOMMU_PORT_INIT("L9_IMG_SMTI_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 5),
	MTK_IOMMU_PORT_INIT("L9_IMG_SMTO_D2_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 6),
	MTK_IOMMU_PORT_INIT("L9_IMG_SMTO_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 7),
	MTK_IOMMU_PORT_INIT("L9_IMG_CRZO_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 8),
	MTK_IOMMU_PORT_INIT("L9_IMG_IMG3O_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 9),
	MTK_IOMMU_PORT_INIT("L9_IMG_VIPI_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 10),
	MTK_IOMMU_PORT_INIT("L9_IMG_SMTI_D5_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 11),
	MTK_IOMMU_PORT_INIT("L9_IMG_TIMGO_D1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 12),
	MTK_IOMMU_PORT_INIT("L9_IMG_UFBC_W0_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 13),
	MTK_IOMMU_PORT_INIT("L9_IMG_UFBC_R0_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 14),
	MTK_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 15),
	MTK_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA0_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 16),
	MTK_IOMMU_PORT_INIT("L9_IMG_WPE_WDMA_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 17),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA0_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 18),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 19),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA2_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 20),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA3_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 21),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA4_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 22),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA5_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 23),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA0_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 24),
	MTK_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA1_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 25),
	MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE6_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 26),
	MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE7_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 27),
	MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE8_MDP", 1,
		SLAVE_L9, 9, TF_LARB_L9, 28),
	/*Larb11 */
	MTK_IOMMU_PORT_INIT("L11_IMG_IMGI_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 0),
	MTK_IOMMU_PORT_INIT("L11_IMG_IMGBI_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 1),
	MTK_IOMMU_PORT_INIT("L11_IMG_DMGI_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 2),
	MTK_IOMMU_PORT_INIT("L11_IMG_DEPI_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 3),
	MTK_IOMMU_PORT_INIT("L11_IMG_ICE_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 4),
	MTK_IOMMU_PORT_INIT("L11_IMG_SMTI_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 5),
	MTK_IOMMU_PORT_INIT("L11_IMG_SMTO_D2_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 6),
	MTK_IOMMU_PORT_INIT("L11_IMG_SMTO_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 7),
	MTK_IOMMU_PORT_INIT("L11_IMG_CRZO_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 8),
	MTK_IOMMU_PORT_INIT("L11_IMG_IMG3O_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 9),
	MTK_IOMMU_PORT_INIT("L11_IMG_VIPI_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 10),
	MTK_IOMMU_PORT_INIT("L11_IMG_SMTI_D5_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 11),
	MTK_IOMMU_PORT_INIT("L11_IMG_TIMGO_D1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 12),
	MTK_IOMMU_PORT_INIT("L11_IMG_UFBC_W0_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 13),
	MTK_IOMMU_PORT_INIT("L11_IMG_UFBC_R0_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 14),
	MTK_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 15),
	MTK_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA0_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 16),
	MTK_IOMMU_PORT_INIT("L11_IMG_WPE_WDMA_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 17),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA0_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 18),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 19),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA2_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 20),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA3_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 21),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA4_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 22),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA5_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 23),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA0_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 24),
	MTK_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA1_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 25),
	MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE6_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 26),
	MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE7_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 27),
	MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE8_DISP", 0,
		SLAVE_L11, 11, TF_LARB_L11, 28),
	/*Larb13 */
	MTK_IOMMU_PORT_INIT("L13_CAM_MRAWI_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 0),
	MTK_IOMMU_PORT_INIT("L13_CAM_MRAWO0_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 1),
	MTK_IOMMU_PORT_INIT("L13_CAM_MRAWO1_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 2),
	MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV1_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 3),
	MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV2_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 4),
	MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV3_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 5),
	MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV4_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 6),
	MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV5_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 7),
	MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV6_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 8),
	MTK_IOMMU_PORT_INIT("L13_CAM_CCUI_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 9),
	MTK_IOMMU_PORT_INIT("L13_CAM_CCUO_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 10),
	MTK_IOMMU_PORT_INIT("L13_CAM_FAKE_MDP", 1,
		SLAVE_L13, 13, TF_LARB_L13, 11),
	/*Larb14 */
	MTK_IOMMU_PORT_INIT("L14_CAM_MRAWI_DISP", 0,
		SLAVE_L14, 14, TF_LARB_L14, 0),
	MTK_IOMMU_PORT_INIT("L14_CAM_MRAWO0_DISP", 0,
		SLAVE_L14, 14, TF_LARB_L14, 1),
	MTK_IOMMU_PORT_INIT("L14_CAM_MRAWO1_DISP", 0,
		SLAVE_L14, 14, TF_LARB_L14, 2),
	MTK_IOMMU_PORT_INIT("L14_CAM_CAMSV0_DISP", 0,
		SLAVE_L14, 14, TF_LARB_L14, 3),
	MTK_IOMMU_PORT_INIT("L14_CAM_CCUI_DISP", 0,
		SLAVE_L14, 14, TF_LARB_L14, 4),
	MTK_IOMMU_PORT_INIT("L14_CAM_CCUO_DISP", 0,
		SLAVE_L14, 14, TF_LARB_L14, 5),
	/*Larb16 */
	MTK_IOMMU_PORT_INIT("L16_CAM_IMGO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 0),
	MTK_IOMMU_PORT_INIT("L16_CAM_RRZO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 1),
	MTK_IOMMU_PORT_INIT("L16_CAM_CQI_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 2),
	MTK_IOMMU_PORT_INIT("L16_CAM_BPCI_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 3),
	MTK_IOMMU_PORT_INIT("L16_CAM_YUVO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 4),
	MTK_IOMMU_PORT_INIT("L16_CAM_UFDI_R2_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 5),
	MTK_IOMMU_PORT_INIT("L16_CAM_RAWI_R2_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 6),
	MTK_IOMMU_PORT_INIT("L16_CAM_RAWI_R3_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 7),
	MTK_IOMMU_PORT_INIT("L16_CAM_AAO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 8),
	MTK_IOMMU_PORT_INIT("L16_CAM_AFO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 9),
	MTK_IOMMU_PORT_INIT("L16_CAM_FLKO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 10),
	MTK_IOMMU_PORT_INIT("L16_CAM_LCESO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 11),
	MTK_IOMMU_PORT_INIT("L16_CAM_CRZO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 12),
	MTK_IOMMU_PORT_INIT("L16_CAM_LTMSO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 13),
	MTK_IOMMU_PORT_INIT("L16_CAM_RSSO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 14),
	MTK_IOMMU_PORT_INIT("L16_CAM_AAHO_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 15),
	MTK_IOMMU_PORT_INIT("L16_CAM_LSCI_R1_A_MDP", 1,
		SLAVE_L16, 16, TF_LARB_L16, 16),
	/*Larb17 */
	MTK_IOMMU_PORT_INIT("L17_CAM_IMGO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 0),
	MTK_IOMMU_PORT_INIT("L17_CAM_RRZO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 1),
	MTK_IOMMU_PORT_INIT("L17_CAM_CQI_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 2),
	MTK_IOMMU_PORT_INIT("L17_CAM_BPCI_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 3),
	MTK_IOMMU_PORT_INIT("L17_CAM_YUVO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 4),
	MTK_IOMMU_PORT_INIT("L17_CAM_UFDI_R2_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 5),
	MTK_IOMMU_PORT_INIT("L17_CAM_RAWI_R2_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 6),
	MTK_IOMMU_PORT_INIT("L17_CAM_RAWI_R3_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 7),
	MTK_IOMMU_PORT_INIT("L17_CAM_AAO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 8),
	MTK_IOMMU_PORT_INIT("L17_CAM_AFO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 9),
	MTK_IOMMU_PORT_INIT("L17_CAM_FLKO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 10),
	MTK_IOMMU_PORT_INIT("L17_CAM_LCESO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 11),
	MTK_IOMMU_PORT_INIT("L17_CAM_CRZO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 12),
	MTK_IOMMU_PORT_INIT("L17_CAM_LTMSO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 13),
	MTK_IOMMU_PORT_INIT("L17_CAM_RSSO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 14),
	MTK_IOMMU_PORT_INIT("L17_CAM_AAHO_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 15),
	MTK_IOMMU_PORT_INIT("L17_CAM_LSCI_R1_B_DISP", 0,
		SLAVE_L17, 17, TF_LARB_L17, 16),
	/*Larb18 */
	MTK_IOMMU_PORT_INIT("L18_CAM_IMGO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 0),
	MTK_IOMMU_PORT_INIT("L18_CAM_RRZO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 1),
	MTK_IOMMU_PORT_INIT("L18_CAM_CQI_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 2),
	MTK_IOMMU_PORT_INIT("L18_CAM_BPCI_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 3),
	MTK_IOMMU_PORT_INIT("L18_CAM_YUVO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 4),
	MTK_IOMMU_PORT_INIT("L18_CAM_UFDI_R2_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 5),
	MTK_IOMMU_PORT_INIT("L18_CAM_RAWI_R2_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 6),
	MTK_IOMMU_PORT_INIT("L18_CAM_RAWI_R3_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 7),
	MTK_IOMMU_PORT_INIT("L18_CAM_AAO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 8),
	MTK_IOMMU_PORT_INIT("L18_CAM_AFO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 9),
	MTK_IOMMU_PORT_INIT("L18_CAM_FLKO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 10),
	MTK_IOMMU_PORT_INIT("L18_CAM_LCESO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 11),
	MTK_IOMMU_PORT_INIT("L18_CAM_CRZO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 12),
	MTK_IOMMU_PORT_INIT("L18_CAM_LTMSO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 13),
	MTK_IOMMU_PORT_INIT("L18_CAM_RSSO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 14),
	MTK_IOMMU_PORT_INIT("L18_CAM_AAHO_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 15),
	MTK_IOMMU_PORT_INIT("L18_CAM_LSCI_R1_C_MDP", 1,
		SLAVE_L18, 18, TF_LARB_L18, 16),
	/*Larb19 */
	MTK_IOMMU_PORT_INIT("L19_IPE_DVS_RDMA_DISP", 0,
		SLAVE_L19, 19, TF_LARB_L19, 0),
	MTK_IOMMU_PORT_INIT("L19_IPE_DVS_WDMA_DISP", 0,
		SLAVE_L19, 19, TF_LARB_L19, 1),
	MTK_IOMMU_PORT_INIT("L19_IPE_DVP_RDMA_DISP", 0,
		SLAVE_L19, 19, TF_LARB_L19, 2),
	MTK_IOMMU_PORT_INIT("L19_IPE_DVP_WDMA_DISP", 0,
		SLAVE_L19, 19, TF_LARB_L19, 3),
	/*Larb20 */
	MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_RDA_DISP", 0,
		SLAVE_L20, 20, TF_LARB_L20, 0),
	MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_RDB_DISP", 0,
		SLAVE_L20, 20, TF_LARB_L20, 1),
	MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_WRA_DISP", 0,
		SLAVE_L20, 20, TF_LARB_L20, 2),
	MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_WRB_DISP", 0,
		SLAVE_L20, 20, TF_LARB_L20, 3),
	MTK_IOMMU_PORT_INIT("L20_IPE_RSC_RDMA0_DISP", 0,
		SLAVE_L20, 20, TF_LARB_L20, 4),
	MTK_IOMMU_PORT_INIT("L20_IPE_RSC_WDMA_DISP", 0,
		SLAVE_L20, 20, TF_LARB_L20, 5),
	/*Larb21 */
	MTK_IOMMU_PORT_INIT("L21_APU_FAKE_CODE", 2,
		SLAVE_APU, 21, TF_APU, 0),
	MTK_IOMMU_PORT_INIT("L21_APU_FAKE_DATA", 2,
		SLAVE_APU, 21, TF_APU, 1),
	MTK_IOMMU_PORT_INIT("L21_APU_FAKE_VLM", 2,
		SLAVE_APU, 21, TF_APU, 2),
	/*Larb22 */
	MTK_IOMMU_PORT_INIT("L22_CCU_DISP", 0,
		SLAVE_CCU_DISP, 22, TF_CCU_DISP, 0),
	/*Larb23 */
	MTK_IOMMU_PORT_INIT("L23_CCU_MDP", 1,
		SLAVE_CCU_MDP, 23, TF_CCU_MDP, 0),

	MTK_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0, 0, 0)
};

/* APU_IOMMU AXI_ID */
#define TF_VP6_0     0x0
#define TF_VP6_1     0x1
#define TF_VP6_2     0x2
#define TF_UP        0x4
#define TF_MDLA0_5  0x5
#define TF_MDLA0_6  0x6
#define TF_MDLA1_7  0x7
#define TF_MDLA1_8  0x8
#define TF_EDMA0     0x9
#define TF_EDMA1     0xA
#define TF_EDMAL0    0xB
#define TF_EDMAL1    0xC
#define TF_ADL       0xD
#define TF_EXTERNAL  0xF

#define MSK_VP6_0     F_MSK(10, 7)
#define MSK_VP6_1     F_MSK(10, 7)
#define MSK_VP6_2     F_MSK(10, 7)
#define MSK_UP        F_MSK(10, 7)
#define MSK_MDLA0_5   F_MSK(10, 7)
#define MSK_MDLA0_6   F_MSK(10, 7)
#define MSK_MDLA1_7   F_MSK(10, 7)
#define MSK_MDLA1_8   F_MSK(10, 7)
#define MSK_EDMA0     F_MSK(10, 7)
#define MSK_EDMA1     F_MSK(10, 7)
#define MSK_EDMAL0    F_MSK(10, 7)
#define MSK_EDMAL1    F_MSK(10, 7)
#define MSK_ADL       F_MSK(10, 7)
#define MSK_EXTERNAL  F_MSK(10, 7)

#define IOMMU_APU_AXI_PORT_NR (14)

static uint32_t vpu_axi_bus_id[IOMMU_APU_AXI_PORT_NR] = {
	TF_VP6_0, TF_VP6_1, TF_VP6_2, TF_UP, TF_MDLA0_5, TF_MDLA0_6,
	TF_MDLA1_7, TF_MDLA1_8, TF_EDMA0, TF_EDMA1, TF_EDMAL0, TF_EDMAL1,
	TF_ADL, TF_EXTERNAL};

static uint32_t vpu_axi_bus_mask[IOMMU_APU_AXI_PORT_NR] = {
	MSK_VP6_0, MSK_VP6_1, MSK_VP6_2, MSK_UP, MSK_MDLA0_5, MSK_MDLA0_6,
	MSK_MDLA1_7, MSK_MDLA1_8, MSK_EDMA0, MSK_EDMA1, MSK_EDMAL0, MSK_EDMAL1,
	MSK_ADL, MSK_EXTERNAL};

static char *vpu_axi_bus_name[IOMMU_APU_AXI_PORT_NR] = {
	"APU_VP6_0", "APU_VP6_1", "APU_VP6_2",
	"APU_uP", "APU_MDLA_0_5", "APU_MDLA_0_6",
	"APU_MDLA_1_7", "APU_MDLA_1_8", "APU_eDMA_0",
	"APU_eDMA_1", "APU_eDMAL_0", "APU_eDMAL_1",
	"APU_ADL", "APU_external_masters"};

#ifndef M4U_PORT_NR
#define M4U_PORT_NR (257)
#endif
#endif
